Hardware verification language
Encyclopedia
A Hardware Verification Language, or HVL, is a programming language used to verify the designs of electronic circuits written in a hardware description language
. HVLs typically include features of a high-level programming language
like C++
or Java
as well as features for easy bit-level manipulation similar to those found in HDLs
. Many HVLs will provide constrained random stimulus generation, and functional coverage constructs to assist with complex hardware verification.
SystemVerilog
, OpenVera
, e
, and SystemC
are the most commonly used HVLs. SystemVerilog
attempts to combine HDL and HVL constructs into a single standard.
Hardware description language
In electronics, a hardware description language or HDL is any language from a class of computer languages, specification languages, or modeling languages for formal description and design of electronic circuits, and most-commonly, digital logic...
. HVLs typically include features of a high-level programming language
High-level programming language
A high-level programming language is a programming language with strong abstraction from the details of the computer. In comparison to low-level programming languages, it may use natural language elements, be easier to use, or be from the specification of the program, making the process of...
like C++
C++
C++ is a statically typed, free-form, multi-paradigm, compiled, general-purpose programming language. It is regarded as an intermediate-level language, as it comprises a combination of both high-level and low-level language features. It was developed by Bjarne Stroustrup starting in 1979 at Bell...
or Java
Java (programming language)
Java is a programming language originally developed by James Gosling at Sun Microsystems and released in 1995 as a core component of Sun Microsystems' Java platform. The language derives much of its syntax from C and C++ but has a simpler object model and fewer low-level facilities...
as well as features for easy bit-level manipulation similar to those found in HDLs
Hardware description language
In electronics, a hardware description language or HDL is any language from a class of computer languages, specification languages, or modeling languages for formal description and design of electronic circuits, and most-commonly, digital logic...
. Many HVLs will provide constrained random stimulus generation, and functional coverage constructs to assist with complex hardware verification.
SystemVerilog
SystemVerilog
In the semiconductor and electronic design industry, SystemVerilog is a combined Hardware Description Language and Hardware Verification Language based on extensions to Verilog.-History:...
, OpenVera
OpenVera
OpenVera is a dead Hardware Verification Language developed, and managed by Synopsys.OpenVera is an interoperable, open hardware verification language for testbench creation. The OpenVera language was used as the basis for the advanced verification features in the IEEE Std...
, e
E (verification language)
e is a hardware verification language which is tailored to implementing highly flexible and reusable verification testbenches.- History :...
, and SystemC
SystemC
SystemC is a set of C++ classes and macros which provide an event-driven simulation kernel in C++ . These facilities enable a designer to simulate concurrent processes, each described using plain C++ syntax...
are the most commonly used HVLs. SystemVerilog
SystemVerilog
In the semiconductor and electronic design industry, SystemVerilog is a combined Hardware Description Language and Hardware Verification Language based on extensions to Verilog.-History:...
attempts to combine HDL and HVL constructs into a single standard.
See also
- OpenVeraOpenVeraOpenVera is a dead Hardware Verification Language developed, and managed by Synopsys.OpenVera is an interoperable, open hardware verification language for testbench creation. The OpenVera language was used as the basis for the advanced verification features in the IEEE Std...
- eE (verification language)e is a hardware verification language which is tailored to implementing highly flexible and reusable verification testbenches.- History :...
- SystemCSystemCSystemC is a set of C++ classes and macros which provide an event-driven simulation kernel in C++ . These facilities enable a designer to simulate concurrent processes, each described using plain C++ syntax...
- SystemVerilogSystemVerilogIn the semiconductor and electronic design industry, SystemVerilog is a combined Hardware Description Language and Hardware Verification Language based on extensions to Verilog.-History:...
- Property Specification LanguageProperty Specification LanguageProperty Specification Language is a language developed by Accellera for specifying properties or assertions about hardware designs. The properties can then be simulated or formally verified. Since September 2004 the standardization on the language has been done in IEEE 1850 working group...