Esterel Studio is a design environment based on the Esterel

Esterel

Esterel is a synchronous programming language for the development of complex reactive systems. The imperative programming style of Esterel allows the simple expression of parallelism and preemption...

 language. It is optimized for hardware IP

IP address

An Internet Protocol address is a numerical label assigned to each device participating in a computer network that uses the Internet Protocol for communication. An IP address serves two principal functions: host or network interface identification and location addressing...

s (such as DMA

Direct memory access

Direct memory access is a feature of modern computers that allows certain hardware subsystems within the computer to access system memory independently of the central processing unit ....

s, protocols, cache controllers, I/O subsystems, etc.) dedicated at capturing formal design specifications, enabling formal verification of properties early in the design phase, and automating the production of synthesizable RTL

Register Transfer Language

In computer science, register transfer language is a term used to describe a kind of intermediate representation that is very close to assembly language, such as that which is used in a compiler. Academic papers and textbooks also often use a form of RTL as an architecture-neutral assembly language...

 (VHDL and Verilog

Verilog

In the semiconductor and electronic design industry, Verilog is a hardware description language used to model electronic systems. Verilog HDL, not to be confused with VHDL , is most commonly used in the design, verification, and implementation of digital logic chips at the register-transfer level...

), both for prototyping and production purposes.

Features

• Formal
  Formal specification
  In computer science, a formal specification is a mathematical description of software or hardware that may be used to develop an implementation. It describes what the system should do, not how the system should do it...
  
   executable specifications.
• Verification of properties and assertions.
• synchronous
  Synchronous programming language
  A synchronous programming language is a computer programming language optimized for programming reactive systems, systems that are often interrupted and must respond quickly. Many such systems are also called realtime systems, and are found often in embedded uses. The term 'reactive' is chosen to...
  
   dataflow design.
• Generate specification in VHDL or Verilog
  Verilog
  In the semiconductor and electronic design industry, Verilog is a hardware description language used to model electronic systems. Verilog HDL, not to be confused with VHDL , is most commonly used in the design, verification, and implementation of digital logic chips at the register-transfer level...
  
   formats.
• Generate C
  C (programming language)
  C is a general-purpose computer programming language developed between 1969 and 1973 by Dennis Ritchie at the Bell Telephone Laboratories for use with the Unix operating system....
  
  , C++
  C++
  C++ is a statically typed, free-form, multi-paradigm, compiled, general-purpose programming language. It is regarded as an intermediate-level language, as it comprises a combination of both high-level and low-level language features. It was developed by Bjarne Stroustrup starting in 1979 at Bell...
  
  , or SystemC
  SystemC
  SystemC is a set of C++ classes and macros which provide an event-driven simulation kernel in C++ . These facilities enable a designer to simulate concurrent processes, each described using plain C++ syntax...
  
   code.
• ECO
  ECO (Domain Driven Design)
  ECO , is a software framework suited for Domain-Driven-Design from , designed to increase productivity by utilizing facilities such as Object-relational mapping for persisting domain objects, UML models for domain classes and executable State Machines for behavior control defined in UML notation...
  
  support.

External links

Esterel Studio web page