DREAM (software)
Encyclopedia
The Distributed Real-time Embedded Analysis Method (DREAM) is a platform-independent open-source tool for the verification
and analysis of distributed
real-time
and embedded
(DRE) systems which focuses on the practical application of formal verification
and timing analysis to real-time middleware
. DREAM supports formal verification of scheduling based on task timed automata
using the Uppaal model checker and the Verimag IF toolset as well as the random testing of real-time components using a discrete event simulator. DREAM is developed at the Center for Embedded Computer Systems at the University of California, Irvine
, in cooperation with researchers from Vanderbilt University
.
Verification
The word verification may refer to:* Verification and validation, in engineering or quality management systems, it is the act of reviewing, inspecting or testing, in order to establish and document that a product, service or system meets regulatory or technical standards.* Verification , in the...
and analysis of distributed
Distributed computing
Distributed computing is a field of computer science that studies distributed systems. A distributed system consists of multiple autonomous computers that communicate through a computer network. The computers interact with each other in order to achieve a common goal...
real-time
Real-time computing
In computer science, real-time computing , or reactive computing, is the study of hardware and software systems that are subject to a "real-time constraint"— e.g. operational deadlines from event to system response. Real-time programs must guarantee response within strict time constraints...
and embedded
Embedded system
An embedded system is a computer system designed for specific control functions within a larger system. often with real-time computing constraints. It is embedded as part of a complete device often including hardware and mechanical parts. By contrast, a general-purpose computer, such as a personal...
(DRE) systems which focuses on the practical application of formal verification
Formal verification
In the context of hardware and software systems, formal verification is the act of proving or disproving the correctness of intended algorithms underlying a system with respect to a certain formal specification or property, using formal methods of mathematics .- Usage :Formal verification can be...
and timing analysis to real-time middleware
Middleware
Middleware is computer software that connects software components or people and their applications. The software consists of a set of services that allows multiple processes running on one or more machines to interact...
. DREAM supports formal verification of scheduling based on task timed automata
Automata
Automata is the plural form of automaton, a self-operating machine. It may also refer to:* "Automata", a short story by E. T. A. Hoffmann* "Automata", a hardboiled science fiction crime series by Penny Arcade...
using the Uppaal model checker and the Verimag IF toolset as well as the random testing of real-time components using a discrete event simulator. DREAM is developed at the Center for Embedded Computer Systems at the University of California, Irvine
University of California, Irvine
The University of California, Irvine , founded in 1965, is one of the ten campuses of the University of California, located in Irvine, California, USA...
, in cooperation with researchers from Vanderbilt University
Vanderbilt University
Vanderbilt University is a private research university located in Nashville, Tennessee, United States. Founded in 1873, the university is named for shipping and rail magnate "Commodore" Cornelius Vanderbilt, who provided Vanderbilt its initial $1 million endowment despite having never been to the...
.