CDC Cyber
Encyclopedia
The CDC Cyber range of mainframe
-class supercomputer
s were the primary products of Control Data Corporation
(CDC) during the 1970s and 1980s. In their day, they were the computer architecture of choice for scientific and mathematically intensive computing. They were used for modeling fluid flow, material science stress analysis, electrochemical machining analysis, probabilistic analysis, energy and academic computing, radiation shielding modeling, and other applications.
Primarily aimed at large office applications instead of the traditional supercomputer tasks, some of the Cyber machines nevertheless included basic vector instructions
for added performance in "traditional" CDC roles.
and CDC 7600
series and therefore shared almost all of the earlier architecture's characteristics. The Cyber-70 series was a minor upgrade from the earlier systems. The Cyber-170 series represented CDCs move from discrete electronic components and core memory to integrated circuits and semiconductor memory
. The Cyber-170/700 series was a late-1970s refresh of the Cyber-170 line.
The central processor
(CPU) and central memory (CM) operated in units of 60-bit words. In CDC lingo, the term "byte" referred to 12-bit entities (which coincided with the word size used by the peripheral processors). Characters were six bits, operation codes were six bits, and central memory addresses were 18 bits. Central processor instructions were either 15 bits or 30 bits.
The 18-bit addressing inherent to the Cyber 170 series imposed a limit of 262,144 (256K) words of main memory, which was semiconductor
memory in this series. The central processor had no I/O instructions, relying upon the peripheral processor (PP) units to do I/O.
A Cyber 170-series system consisted of one or two CPUs
that ran at either 25 or 40 MHz, and was equipped with 10, 14, 17, or 20 peripheral processors (PP), and up to 24 high-performance channels for high-speed I/O
. Due to the relatively slow memory reference times of the CPU (in some models, memory reference instructions were slower than floating point divides), the higher end CPUs (e.g., Cyber-74, Cyber-76, Cyber-175, and Cyber-176) were equipped with 8 or 12 words of high-speed memory used as an instruction cache. Any loop that fit into the cache (which was usually called in-stack) would run without referencing main memory for instruction fetch. The lower-end models did not contain an instruction stack. However since up to four instructions were packed into each 60-bit word, some degree of prefetching was inherent in the design.
As with predecessor systems, the Cyber 170 series had eight 18-bit address registers
(A0 through A7), eight 18-bit index registers (B0 through B7), and eight 60-bit operand registers (X0 through X7). Seven of the A registers were tied to their corresponding X register. Setting A1 through A5 read that address and fetched it into the corresponding X1 through X5 register. Likewise, setting register A6 or A7 wrote the corresponding X6 or X7 register to central memory at the address written to the A register. A0 was effectively a scratch register.
The higher end CPUs consisted of multiple functional units
(e.g., shift, increment, floating add) which allowed some degree of parallel execution of instructions. This parallelism allowed assembly programmers to minimize the effects of the system's slow memory fetch time by pre-fetching data from central memory well before that data was needed. By interleaving independent instructions between the memory fetch instruction and the instructions manipulating the fetched operand, the time occupied by the memory fetch could be used for other computation. With this technique, coupled with the handcrafting of tight loops that fit within the instruction stack, a skilled Cyber assembly programmer could write extremely efficient code that made the most of the power of the hardware.
The peripheral processor subsystem used a technique known as barrel and slot to share the execution unit; each PP had its own memory and registers, but the processor (the slot) itself executed one instruction from each PP in turn (the barrel). This is a crude form of hardware multiprogramming
. The peripheral processors had 4096 bytes of 12-bit memory words and an 18-bit accumulator register. Each PP had access to all I/O
channels and all of the system's central memory (CM) in addition to the PP's own memory. The PP instruction set lacked, for example, extensive arithmetic capabilities and did not run user code; the peripheral processor subsystem's purpose was to process I/O and thereby free the more powerful central processor unit(s) to running user computations.
A feature of the 'lower Cyber' CPUs was the Compare Move Unit (CMU). It provided four additional instructions intended to aid text processing applications. In an unusual departure from the rest of the 15- and 30-bit instructions, these were 60-bit instructions (3 actually used all 60 bits, the other used 30 bits, but its alignment required 60 bits to be used). The instructions were move a short string, move a long string, compare strings, and compare a collated string. They operated on 6-bit fields (numbered 1 through 10) in central memory. For example, a single instruction could specify "move the 72 character string starting at word 1000 character 3 to location 2000 character 9". The CMU hardware was not included in the higher-end Cyber CPUs, because handcoded loops could run as fast or faster than the CMU instructions.
Later systems typically ran CDC's NOS
(Network Operating System). Version 1 of NOS continued to be updated until about 1981; NOS version 2 was released early 1982. Besides NOS, the only other operating systems commonly used on the 170 series was NOS/BE or its predecessor SCOPE, a product of CDC's Sunnyvale division. These operating systems provided time sharing of batch and interactive applications. The predecessor to NOS was Kronos which was in common use up until 1975 or so. Due to the strong dependency of developed applications on the particular installation's character set, many installations chose to run the older operating systems than convert their applications. Other installations would patch newer versions of the operating system to use the older character set to maintain application compatibility.
. The joint venture was abandoned in 1976, with CDC continuing system development and renaming the Cyber 80 as Cyber 180. The first machines of the series were announced in 1982 and the product announcement for the NOS/VE operating system occurred in 1983.
As the computing world standardized to an eight-bit byte
size, CDC customers started pushing for the Cyber machines to do the same. The result was a new series of systems that could operate in both 60- and 64-bit modes. The 64-bit
operating system was called NOS/VE, and supported the virtual memory
capabilities of the hardware. The older 60-bit operating systems, NOS
and NOS/BE, could run in a special address space for compatibility with the older systems.
The true 180-mode machines were microcoded processors that could, and did, support both instruction sets simultaneously. Their hardware was completely different from the earlier 6000/70/170 machines. The small 170-mode exchange package was mapped into the much larger 180-mode exchange package; within the 180-mode exchange package, there was a VMID—virtual machine identifier—that determined whether the 8/16/64-bit twos complement 180 instruction set or the 12/60-bit ones complement 170 instruction set was executed.
There were 3 true 180s in the initial lineup, codenamed P1, P2, P3. P2 & P3 were larger water-cooled designs. The P2 was designed in Mississauga, by the same team who later designed the smaller P1, and the P3 was designed in Arden Hills, Minnesota
. The P1 was a novel air-cooled, 60-board cabinet designed by a group in Mississauga, Ontario
; the P1 ran on 60 Hz current (no motor-generator sets needed). A fourth high-end 180 model 990 (codenamed THETA) was also under development in Arden Hills.
The 180s were initially marketed as 170/8xx machines with no mention of the new 8/64-bit system inside. However, the primary control program was a 180-mode program known as EI (Environmental Interface). The 170 operating system (NOS) utilized a single, large, fixed page within the main memory. There were a few clues that an alert user could pick up on, such as the "building page tables" message that flashed on the operator's console at startup and deadstart panels with 16 (instead of 12) toggle switches per PP word on the P2 & P3.
The peripheral processors in the true 180s were always 16-bit machines with the sign bit determining whether a 16/64 bit or 12/60 bit PP instruction was being executed. The single word I/O instructions in the PPs were always 16-bit instructions, so at deadstart the PPs could set up the proper environment to run both EI plus NOS and the customer's existing 170-mode software. To hide this process from the customer, earlier in the 1980s CDC had ceased distribution of the source code for its DDS (Deadstart Diagnostic Sequence) package and turned it into the proprietary CTI (Common Tests & Initialization) package.
The initial 170/800 lineup was: 170/825 (P1), 170/835 (P2), 170/855 (P3), 170/865 and 170/875. The 825 was released initially after some delay loops had been added to its microcode; it seemed the design folks in Toronto had done a little too well and it was too close to the P2 in performance. The 865 and 875 models were revamped 170/760 heads (1 or 2 processors with 6600/7600-style parallel functional units) with larger memories. The 865 used normal 170 memory; the 875 took its faster main processor memory from the Cyber 205 line.
A year or two after the initial release, CDC announced the 800-series' true capabilities to its customers, and the true 180s were relabeled as the 180/825 (P1), 180/835 (P2), and 180/855 (P3). At some point the model 815 was introduced with the delayed microcode and the faster microcode was restored to the model 825. Eventually the THETA was released as the Cyber 990.
architecture. The STAR was an entirely new 64-bit design with virtual memory
and vector processing
instructions added for high performance on a certain class of math tasks. The STAR's vector pipeline was a memory to memory pipe, which supported vector lengths of up to 65,536 elements. Unfortunately, the latencies of the vector pipeline were very long, so peak speed was approached only when very long vectors were used. The scalar processor was relatively slow in comparison to the CDC 7600
. As such, the original STAR proved to be a great disappointment when it was released (see Amdahl's Law
). However many of its problems seemed solvable. Best estimates claim that three STAR-100 systems were delivered.
In the late 1970s, CDC addressed some of these issues with the Cyber 203. The new name kept with their new branding, and perhaps to distance itself from the STAR's failure. The Cyber 203 contained redesigned scalar processing and loosely coupled I/O design, but retained the STAR's vector pipeline. Best estimates claim that two Cyber 203s were delivered and/or upgraded from STAR-100s.
In 1980, the successor to the Cyber 203, the Cyber 205 was announced. The UK Meteorological Office at Bracknell, England was the first customer and they received their Cyber 205 in 1981. The Cyber 205 replaced the STAR vector pipeline with redesigned vector pipelines: both scalar and vector units utilized ECL
gate array
ICs and were cooled with Freon. Cyber 205 systems were available with two or four vector pipelines, with the four-pipe version theoretically delivering 400 64-bit MFLOPs and 800 32-bit MFLOPs. These speeds were rarely seen in practice other than by handcrafted assembly language
. The ECL gate array ICs contained 168 logic gates each, with the clock tree networks being tuned by hand-crafted coax length adjustment. It is worth noting that the instruction set would be considered V-CISC
(very complex instruction set) among modern processors. Many specialized operations facilitated hardware searches, matrix mathematics, and special instructions that would enable decryption. The original Cyber 205 was renamed to Cyber 205 Series 400 in 1983 when the Cyber 205 Series 600 was introduced. The Series 600 differed in memory technology and packaging but was otherwise the same. The Cyber 205 architecture evolved into the ETA10
as the design team spun off into ETA Systems
in September 1983. A single four-pipe Cyber 205 was installed. All other sites appear to be two-pipe installations with final count to be determined.
Also there was a Cyber 250 which was scheduled for release in 1987 priced at $20 million; it was later renamed the ETA30 after ETA Systems was absorbed back into CDC.
The FP control unit had a hardware network for conditional microinstruction execution, with four mask registers and a condition-hold register; three bits in the microinstruction format select among nearly 50 conditions for determining execution, including result sign and overflow, I/O conditions, and loop control:
an ancestor to the ARM architecture
.
At least 21 Cyberplus multiprocessor
installations were operational in 1986. These parallel processing systems include from 1 to 256 Cyberplus processors providing 250 MFLOPS each, which are connected to an existing Cyber system via a direct memory interconnect architecture (MIA), this was available on NOS 2.2 for the Cyber 170/835, 845, 855 and 180/990 models.
Each physical Cyberplus processor unit was:
Software that was bundled with the Cyberplus was:
Some sites using the Cyberplus were the University of Georgia
and the Gesellschaft für Trendanalysen (GfTA) (Association for Trend Analyses) in Germany.
A fully configured 256 processor Cyberplus system would have a theoretical performance of 64 GFLOPS and would weigh 256 tonnes.
minicomputer. It was mostly used in real-time environments. One noteworthy application is as the basis of the 2550 - a communications processor used by CDC 6000 series
and Cyber 70/Cyber 170 mainframes. The 2550 was a product of CDC's Communications Systems Division, in Santa Ana, California (STAOPS). STAOPS also produced another communication processor (CP), used in networks hosted by IBM mainframes. This M1000 CP, later renamed C1000, came from an acquisition of Marshall MDM Communications. A 3-board set was added to the Cyber 18 to create the 2550.
The Cyber 18 was generally programmed in Pascal
and assembly language
; FORTRAN
, BASIC
, and RPG II were also available. Operating systems included RTOS (Real-Time Operating System), MSOS 5 (Mass Storage Operating System), and TIMESHARE
3 (time-sharing
system).
"Cyber 18-17" was just a new name for the System 17, based on the 1784 processor. Other Cyber 18s (Cyber 18-05, 18-10, 18-20, and 18-30) had microprogrammable
processors with up to 128K words of memory, four additional general registers, and an enhanced instruction set. The Cyber 18-30 had dual processors. A special version of the Cyber 18, known as the MP32, that was 32-bit instead of 16-bit was created for the National Security Agency for crypto-analysis work. The Soviet Union tried to buy several of these systems and they were being built when the US Government cancelled the order. The parts for the MP32 were absorbed into the Cyber 18 production. One of the uses of the Cyber 18 was monitoring the Alaskan Pipeline.
M1000 / C1000 later renamed Cyber 1000 was used as a message store and forward system used by the Federal Reserve System. A version of the Cyber 1000 with its hard drive removed was used by Bell Telephone. This was a RISC processor (Reduced Instruction Set Computer). An improved version known as the Cyber 1000-2 with the Line Termination Sub-System added 256 Zilog Z80 microprocessors. The Bell Operating Companies purchased large numbers of these systems in the mid to late 1980s for data communications. In the late 1980s the XN10 was released with an improved processor (a direct memory access instruction was added) as well as a size reduction from two cabinets to one. The XN20 was an improved version of the XN10 with a much smaller footprint. The Line Termination Sub-System was redesigned to use the improved Z180 microprocessor (the Buffer Controller card, Programmable Line Controller card and two Communication Line Interface cards were incorporated on to a single card). The XN20 was in pre-production stage when the Communication Systems Division was shut down in 1992.
Jack Ralph was the chief architect of the Cyber 1000-2, XN-10 and XN-20 systems. Dan Nay was the chief engineer of the XN-20.
Mainframe computer
Mainframes are powerful computers used primarily by corporate and governmental organizations for critical applications, bulk data processing such as census, industry and consumer statistics, enterprise resource planning, and financial transaction processing.The term originally referred to the...
-class supercomputer
Supercomputer
A supercomputer is a computer at the frontline of current processing capacity, particularly speed of calculation.Supercomputers are used for highly calculation-intensive tasks such as problems including quantum physics, weather forecasting, climate research, molecular modeling A supercomputer is a...
s were the primary products of Control Data Corporation
Control Data Corporation
Control Data Corporation was a supercomputer firm. For most of the 1960s, it built the fastest computers in the world by far, only losing that crown in the 1970s after Seymour Cray left the company to found Cray Research, Inc....
(CDC) during the 1970s and 1980s. In their day, they were the computer architecture of choice for scientific and mathematically intensive computing. They were used for modeling fluid flow, material science stress analysis, electrochemical machining analysis, probabilistic analysis, energy and academic computing, radiation shielding modeling, and other applications.
Models
The Cyber line included five very different models of computer:- The 70 and 170 series based on the architecture of the CDC 6600CDC 6600The CDC 6600 was a mainframe computer from Control Data Corporation, first delivered in 1964. It is generally considered to be the first successful supercomputer, outperforming its fastest predecessor, IBM 7030 Stretch, by about three times...
and CDC 7600CDC 7600The CDC 7600 was the Seymour Cray-designed successor to the CDC 6600, extending Control Data's dominance of the supercomputer field into the 1970s. The 7600 ran at 36.4 MHz and had a 65 Kword primary memory using core and variable-size secondary memory... - The 180 series developed by a team in Canada
- The 200 series based on the CDC STAR-100CDC STAR-100The STAR-100 was a vector supercomputer designed, manufactured, and marketed by Control Data Corporation . It was one of the first machines to use a vector processor to improve performance on appropriate scientific applications....
- The Cyberplus or Advanced Flexible Processor (AFP)
- The Cyber-18 minicomputer based on the CDC 1700CDC 1700The CDC 1700 was a 16-bit word minicomputer, manufactured by the Control Data Corporation with deliveries beginning in May, 1966. The 1700 used ones' complement arithmetic and an ASCII-based character set, and supported memory write protection on an individual word basis...
Primarily aimed at large office applications instead of the traditional supercomputer tasks, some of the Cyber machines nevertheless included basic vector instructions
Vector processor
A vector processor, or array processor, is a central processing unit that implements an instruction set containing instructions that operate on one-dimensional arrays of data called vectors. This is in contrast to a scalar processor, whose instructions operate on single data items...
for added performance in "traditional" CDC roles.
Cyber 70 and 170 series
The Cyber 70 and 170 architectures were successors to the earlier CDC 6600CDC 6600
The CDC 6600 was a mainframe computer from Control Data Corporation, first delivered in 1964. It is generally considered to be the first successful supercomputer, outperforming its fastest predecessor, IBM 7030 Stretch, by about three times...
and CDC 7600
CDC 7600
The CDC 7600 was the Seymour Cray-designed successor to the CDC 6600, extending Control Data's dominance of the supercomputer field into the 1970s. The 7600 ran at 36.4 MHz and had a 65 Kword primary memory using core and variable-size secondary memory...
series and therefore shared almost all of the earlier architecture's characteristics. The Cyber-70 series was a minor upgrade from the earlier systems. The Cyber-170 series represented CDCs move from discrete electronic components and core memory to integrated circuits and semiconductor memory
Semiconductor memory
Semiconductor memory is an electronic data storage device, often used as computer memory, implemented on a semiconductor-based integrated circuit. Examples of semiconductor memory include non-volatile memory such as Read-only memory , magnetoresistive random access memory , and flash memory...
. The Cyber-170/700 series was a late-1970s refresh of the Cyber-170 line.
The central processor
Central processing unit
The central processing unit is the portion of a computer system that carries out the instructions of a computer program, to perform the basic arithmetical, logical, and input/output operations of the system. The CPU plays a role somewhat analogous to the brain in the computer. The term has been in...
(CPU) and central memory (CM) operated in units of 60-bit words. In CDC lingo, the term "byte" referred to 12-bit entities (which coincided with the word size used by the peripheral processors). Characters were six bits, operation codes were six bits, and central memory addresses were 18 bits. Central processor instructions were either 15 bits or 30 bits.
The 18-bit addressing inherent to the Cyber 170 series imposed a limit of 262,144 (256K) words of main memory, which was semiconductor
Semiconductor
A semiconductor is a material with electrical conductivity due to electron flow intermediate in magnitude between that of a conductor and an insulator. This means a conductivity roughly in the range of 103 to 10−8 siemens per centimeter...
memory in this series. The central processor had no I/O instructions, relying upon the peripheral processor (PP) units to do I/O.
A Cyber 170-series system consisted of one or two CPUs
Central processing unit
The central processing unit is the portion of a computer system that carries out the instructions of a computer program, to perform the basic arithmetical, logical, and input/output operations of the system. The CPU plays a role somewhat analogous to the brain in the computer. The term has been in...
that ran at either 25 or 40 MHz, and was equipped with 10, 14, 17, or 20 peripheral processors (PP), and up to 24 high-performance channels for high-speed I/O
I/O
I/O may refer to:* Input/output, a system of communication for information processing systems* Input-output model, an economic model of flow prediction between sectors...
. Due to the relatively slow memory reference times of the CPU (in some models, memory reference instructions were slower than floating point divides), the higher end CPUs (e.g., Cyber-74, Cyber-76, Cyber-175, and Cyber-176) were equipped with 8 or 12 words of high-speed memory used as an instruction cache. Any loop that fit into the cache (which was usually called in-stack) would run without referencing main memory for instruction fetch. The lower-end models did not contain an instruction stack. However since up to four instructions were packed into each 60-bit word, some degree of prefetching was inherent in the design.
As with predecessor systems, the Cyber 170 series had eight 18-bit address registers
Processor register
In computer architecture, a processor register is a small amount of storage available as part of a CPU or other digital processor. Such registers are addressed by mechanisms other than main memory and can be accessed more quickly...
(A0 through A7), eight 18-bit index registers (B0 through B7), and eight 60-bit operand registers (X0 through X7). Seven of the A registers were tied to their corresponding X register. Setting A1 through A5 read that address and fetched it into the corresponding X1 through X5 register. Likewise, setting register A6 or A7 wrote the corresponding X6 or X7 register to central memory at the address written to the A register. A0 was effectively a scratch register.
The higher end CPUs consisted of multiple functional units
Execution unit
In computer engineering, an execution unit is a part of a CPU that performs the operations and calculations called for by the Branch Unit, which receives data from the CPU...
(e.g., shift, increment, floating add) which allowed some degree of parallel execution of instructions. This parallelism allowed assembly programmers to minimize the effects of the system's slow memory fetch time by pre-fetching data from central memory well before that data was needed. By interleaving independent instructions between the memory fetch instruction and the instructions manipulating the fetched operand, the time occupied by the memory fetch could be used for other computation. With this technique, coupled with the handcrafting of tight loops that fit within the instruction stack, a skilled Cyber assembly programmer could write extremely efficient code that made the most of the power of the hardware.
The peripheral processor subsystem used a technique known as barrel and slot to share the execution unit; each PP had its own memory and registers, but the processor (the slot) itself executed one instruction from each PP in turn (the barrel). This is a crude form of hardware multiprogramming
Multiprogramming
Computer multiprogramming is the allocation of a computer system and its resources to more than one concurrent application, job or user ....
. The peripheral processors had 4096 bytes of 12-bit memory words and an 18-bit accumulator register. Each PP had access to all I/O
I/O
I/O may refer to:* Input/output, a system of communication for information processing systems* Input-output model, an economic model of flow prediction between sectors...
channels and all of the system's central memory (CM) in addition to the PP's own memory. The PP instruction set lacked, for example, extensive arithmetic capabilities and did not run user code; the peripheral processor subsystem's purpose was to process I/O and thereby free the more powerful central processor unit(s) to running user computations.
A feature of the 'lower Cyber' CPUs was the Compare Move Unit (CMU). It provided four additional instructions intended to aid text processing applications. In an unusual departure from the rest of the 15- and 30-bit instructions, these were 60-bit instructions (3 actually used all 60 bits, the other used 30 bits, but its alignment required 60 bits to be used). The instructions were move a short string, move a long string, compare strings, and compare a collated string. They operated on 6-bit fields (numbered 1 through 10) in central memory. For example, a single instruction could specify "move the 72 character string starting at word 1000 character 3 to location 2000 character 9". The CMU hardware was not included in the higher-end Cyber CPUs, because handcoded loops could run as fast or faster than the CMU instructions.
Later systems typically ran CDC's NOS
NOS (software)
NOS was an operating system with time-sharing capabilities, written by Control Data Corporation in the 1970s....
(Network Operating System). Version 1 of NOS continued to be updated until about 1981; NOS version 2 was released early 1982. Besides NOS, the only other operating systems commonly used on the 170 series was NOS/BE or its predecessor SCOPE, a product of CDC's Sunnyvale division. These operating systems provided time sharing of batch and interactive applications. The predecessor to NOS was Kronos which was in common use up until 1975 or so. Due to the strong dependency of developed applications on the particular installation's character set, many installations chose to run the older operating systems than convert their applications. Other installations would patch newer versions of the operating system to use the older character set to maintain application compatibility.
Cyber 180 series
Cyber 180 development began in the Advanced Systems Laboratory, a joint CDC/NCR development venture started in 1973. The machine family was originally called IPL (Integrated Product Line) and was intended to be a virtual memory replacement for the NCR 6150 and CDC Cyber 70 product lines. The IPL system was also called the Cyber 80 in development documents. A high-level Pascal like language called SWL (Software Writers Language) was developed for the project with the intent that all languages and the operating system (IPLOS) were going to be written in SWL. SWL was later renamed PASCAL-X and eventually became CybilCybil (computer language)
Cybil the Cyber Implementation Language of the Control Data Network Operating System was a Pascal-like language developed at Control Data Corporation....
. The joint venture was abandoned in 1976, with CDC continuing system development and renaming the Cyber 80 as Cyber 180. The first machines of the series were announced in 1982 and the product announcement for the NOS/VE operating system occurred in 1983.
As the computing world standardized to an eight-bit byte
Byte
The byte is a unit of digital information in computing and telecommunications that most commonly consists of eight bits. Historically, a byte was the number of bits used to encode a single character of text in a computer and for this reason it is the basic addressable element in many computer...
size, CDC customers started pushing for the Cyber machines to do the same. The result was a new series of systems that could operate in both 60- and 64-bit modes. The 64-bit
64-bit
64-bit is a word size that defines certain classes of computer architecture, buses, memory and CPUs, and by extension the software that runs on them. 64-bit CPUs have existed in supercomputers since the 1970s and in RISC-based workstations and servers since the early 1990s...
operating system was called NOS/VE, and supported the virtual memory
Virtual memory
In computing, virtual memory is a memory management technique developed for multitasking kernels. This technique virtualizes a computer architecture's various forms of computer data storage , allowing a program to be designed as though there is only one kind of memory, "virtual" memory, which...
capabilities of the hardware. The older 60-bit operating systems, NOS
NOS (software)
NOS was an operating system with time-sharing capabilities, written by Control Data Corporation in the 1970s....
and NOS/BE, could run in a special address space for compatibility with the older systems.
The true 180-mode machines were microcoded processors that could, and did, support both instruction sets simultaneously. Their hardware was completely different from the earlier 6000/70/170 machines. The small 170-mode exchange package was mapped into the much larger 180-mode exchange package; within the 180-mode exchange package, there was a VMID—virtual machine identifier—that determined whether the 8/16/64-bit twos complement 180 instruction set or the 12/60-bit ones complement 170 instruction set was executed.
There were 3 true 180s in the initial lineup, codenamed P1, P2, P3. P2 & P3 were larger water-cooled designs. The P2 was designed in Mississauga, by the same team who later designed the smaller P1, and the P3 was designed in Arden Hills, Minnesota
Arden Hills, Minnesota
As of the census of 2000, there were 9,652 people, 2,959 households, and 2,228 families residing in the city. The population density was 1,087.3 people per square mile . There were 3,017 housing units at an average density of 339.9 per square mile...
. The P1 was a novel air-cooled, 60-board cabinet designed by a group in Mississauga, Ontario
Ontario
Ontario is a province of Canada, located in east-central Canada. It is Canada's most populous province and second largest in total area. It is home to the nation's most populous city, Toronto, and the nation's capital, Ottawa....
; the P1 ran on 60 Hz current (no motor-generator sets needed). A fourth high-end 180 model 990 (codenamed THETA) was also under development in Arden Hills.
The 180s were initially marketed as 170/8xx machines with no mention of the new 8/64-bit system inside. However, the primary control program was a 180-mode program known as EI (Environmental Interface). The 170 operating system (NOS) utilized a single, large, fixed page within the main memory. There were a few clues that an alert user could pick up on, such as the "building page tables" message that flashed on the operator's console at startup and deadstart panels with 16 (instead of 12) toggle switches per PP word on the P2 & P3.
The peripheral processors in the true 180s were always 16-bit machines with the sign bit determining whether a 16/64 bit or 12/60 bit PP instruction was being executed. The single word I/O instructions in the PPs were always 16-bit instructions, so at deadstart the PPs could set up the proper environment to run both EI plus NOS and the customer's existing 170-mode software. To hide this process from the customer, earlier in the 1980s CDC had ceased distribution of the source code for its DDS (Deadstart Diagnostic Sequence) package and turned it into the proprietary CTI (Common Tests & Initialization) package.
The initial 170/800 lineup was: 170/825 (P1), 170/835 (P2), 170/855 (P3), 170/865 and 170/875. The 825 was released initially after some delay loops had been added to its microcode; it seemed the design folks in Toronto had done a little too well and it was too close to the P2 in performance. The 865 and 875 models were revamped 170/760 heads (1 or 2 processors with 6600/7600-style parallel functional units) with larger memories. The 865 used normal 170 memory; the 875 took its faster main processor memory from the Cyber 205 line.
A year or two after the initial release, CDC announced the 800-series' true capabilities to its customers, and the true 180s were relabeled as the 180/825 (P1), 180/835 (P2), and 180/855 (P3). At some point the model 815 was introduced with the delayed microcode and the faster microcode was restored to the model 825. Eventually the THETA was released as the Cyber 990.
Cyber 200 series
In 1974 CDC introduced the STARCDC STAR-100
The STAR-100 was a vector supercomputer designed, manufactured, and marketed by Control Data Corporation . It was one of the first machines to use a vector processor to improve performance on appropriate scientific applications....
architecture. The STAR was an entirely new 64-bit design with virtual memory
Virtual memory
In computing, virtual memory is a memory management technique developed for multitasking kernels. This technique virtualizes a computer architecture's various forms of computer data storage , allowing a program to be designed as though there is only one kind of memory, "virtual" memory, which...
and vector processing
Vector processor
A vector processor, or array processor, is a central processing unit that implements an instruction set containing instructions that operate on one-dimensional arrays of data called vectors. This is in contrast to a scalar processor, whose instructions operate on single data items...
instructions added for high performance on a certain class of math tasks. The STAR's vector pipeline was a memory to memory pipe, which supported vector lengths of up to 65,536 elements. Unfortunately, the latencies of the vector pipeline were very long, so peak speed was approached only when very long vectors were used. The scalar processor was relatively slow in comparison to the CDC 7600
CDC 7600
The CDC 7600 was the Seymour Cray-designed successor to the CDC 6600, extending Control Data's dominance of the supercomputer field into the 1970s. The 7600 ran at 36.4 MHz and had a 65 Kword primary memory using core and variable-size secondary memory...
. As such, the original STAR proved to be a great disappointment when it was released (see Amdahl's Law
Amdahl's law
Amdahl's law, also known as Amdahl's argument, is named after computer architect Gene Amdahl, and is used to find the maximum expected improvement to an overall system when only part of the system is improved...
). However many of its problems seemed solvable. Best estimates claim that three STAR-100 systems were delivered.
In the late 1970s, CDC addressed some of these issues with the Cyber 203. The new name kept with their new branding, and perhaps to distance itself from the STAR's failure. The Cyber 203 contained redesigned scalar processing and loosely coupled I/O design, but retained the STAR's vector pipeline. Best estimates claim that two Cyber 203s were delivered and/or upgraded from STAR-100s.
In 1980, the successor to the Cyber 203, the Cyber 205 was announced. The UK Meteorological Office at Bracknell, England was the first customer and they received their Cyber 205 in 1981. The Cyber 205 replaced the STAR vector pipeline with redesigned vector pipelines: both scalar and vector units utilized ECL
Emitter-coupled logic
In electronics, emitter-coupled logic , is a logic family that achieves high speed by using an overdriven BJT differential amplifier with single-ended input, whose emitter current is limited to avoid the slow saturation region of transistor operation....
gate array
Gate array
A gate array or uncommitted logic array is an approach to the design and manufacture of application-specific integrated circuits...
ICs and were cooled with Freon. Cyber 205 systems were available with two or four vector pipelines, with the four-pipe version theoretically delivering 400 64-bit MFLOPs and 800 32-bit MFLOPs. These speeds were rarely seen in practice other than by handcrafted assembly language
Assembly language
An assembly language is a low-level programming language for computers, microprocessors, microcontrollers, and other programmable devices. It implements a symbolic representation of the machine codes and other constants needed to program a given CPU architecture...
. The ECL gate array ICs contained 168 logic gates each, with the clock tree networks being tuned by hand-crafted coax length adjustment. It is worth noting that the instruction set would be considered V-CISC
Complex instruction set computer
A complex instruction set computer , is a computer where single instructions can execute several low-level operations and/or are capable of multi-step operations or addressing modes within single instructions...
(very complex instruction set) among modern processors. Many specialized operations facilitated hardware searches, matrix mathematics, and special instructions that would enable decryption. The original Cyber 205 was renamed to Cyber 205 Series 400 in 1983 when the Cyber 205 Series 600 was introduced. The Series 600 differed in memory technology and packaging but was otherwise the same. The Cyber 205 architecture evolved into the ETA10
ETA10
The ETA10 was a line of vector supercomputers designed, manufactured, and marketed by ETA Systems, a spin-off division of Control Data Corporation . The ETA10 was announced in 1986, with the first deliveries made in early 1987...
as the design team spun off into ETA Systems
ETA Systems
ETA Systems was a supercomputer company spun off from Control Data Corporation in the early 1980s in order to regain a footing in the supercomputer business. They successfully delivered an excellent machine, the ETA-10, but lost money continually while doing so...
in September 1983. A single four-pipe Cyber 205 was installed. All other sites appear to be two-pipe installations with final count to be determined.
Also there was a Cyber 250 which was scheduled for release in 1987 priced at $20 million; it was later renamed the ETA30 after ETA Systems was absorbed back into CDC.
Cyberplus or Advanced Flexible Processor (AFP)
Each Cyberplus (aka Advanced Flexible Processor, AFP) is a 16-bit processor with optional 64-bit floating point capabilities and has 256 K or 512 K words of 64-bit memory. The AFP was the successor to the Flexible Processor (FP), whose design development started in 1972 under black-project circumstances targeted at processing radar and photo image data.The FP control unit had a hardware network for conditional microinstruction execution, with four mask registers and a condition-hold register; three bits in the microinstruction format select among nearly 50 conditions for determining execution, including result sign and overflow, I/O conditions, and loop control:
an ancestor to the ARM architecture
ARM architecture
ARM is a 32-bit reduced instruction set computer instruction set architecture developed by ARM Holdings. It was named the Advanced RISC Machine, and before that, the Acorn RISC Machine. The ARM architecture is the most widely used 32-bit ISA in numbers produced...
.
At least 21 Cyberplus multiprocessor
Multiprocessing
Multiprocessing is the use of two or more central processing units within a single computer system. The term also refers to the ability of a system to support more than one processor and/or the ability to allocate tasks between them...
installations were operational in 1986. These parallel processing systems include from 1 to 256 Cyberplus processors providing 250 MFLOPS each, which are connected to an existing Cyber system via a direct memory interconnect architecture (MIA), this was available on NOS 2.2 for the Cyber 170/835, 845, 855 and 180/990 models.
Each physical Cyberplus processor unit was:
- 348 cm wide (465 cm with floating point unit)
- 161 cm deep
- 490 cm high
- 1000 kg weight
Software that was bundled with the Cyberplus was:
- system software
- FORTRAN cross compiler
- MICA (Machine Instruction Cross Assembler)
- Load File Builder Utility
- ECHOS (simulator)
- Debug facility
- Dump utility
- Dump analyzer utility
- Maintenance software
Some sites using the Cyberplus were the University of Georgia
University of Georgia
The University of Georgia is a public research university located in Athens, Georgia, United States. Founded in 1785, it is the oldest and largest of the state's institutions of higher learning and is one of multiple schools to claim the title of the oldest public university in the United States...
and the Gesellschaft für Trendanalysen (GfTA) (Association for Trend Analyses) in Germany.
A fully configured 256 processor Cyberplus system would have a theoretical performance of 64 GFLOPS and would weigh 256 tonnes.
Cyber 18
The Cyber 18 was a 16-bit minicomputer which was a successor to the CDC 1700CDC 1700
The CDC 1700 was a 16-bit word minicomputer, manufactured by the Control Data Corporation with deliveries beginning in May, 1966. The 1700 used ones' complement arithmetic and an ASCII-based character set, and supported memory write protection on an individual word basis...
minicomputer. It was mostly used in real-time environments. One noteworthy application is as the basis of the 2550 - a communications processor used by CDC 6000 series
CDC 6000 series
The CDC 6000 series was a family of mainframe computers manufactured by Control Data Corporation in the 1960s. It consisted of CDC 6400, CDC 6500, CDC 6600 and CDC 6700 computers, which all were extremely rapid and efficient for their time...
and Cyber 70/Cyber 170 mainframes. The 2550 was a product of CDC's Communications Systems Division, in Santa Ana, California (STAOPS). STAOPS also produced another communication processor (CP), used in networks hosted by IBM mainframes. This M1000 CP, later renamed C1000, came from an acquisition of Marshall MDM Communications. A 3-board set was added to the Cyber 18 to create the 2550.
The Cyber 18 was generally programmed in Pascal
Pascal (programming language)
Pascal is an influential imperative and procedural programming language, designed in 1968/9 and published in 1970 by Niklaus Wirth as a small and efficient language intended to encourage good programming practices using structured programming and data structuring.A derivative known as Object Pascal...
and assembly language
Assembly language
An assembly language is a low-level programming language for computers, microprocessors, microcontrollers, and other programmable devices. It implements a symbolic representation of the machine codes and other constants needed to program a given CPU architecture...
; FORTRAN
Fortran
Fortran is a general-purpose, procedural, imperative programming language that is especially suited to numeric computation and scientific computing...
, BASIC
BASIC
BASIC is a family of general-purpose, high-level programming languages whose design philosophy emphasizes ease of use - the name is an acronym from Beginner's All-purpose Symbolic Instruction Code....
, and RPG II were also available. Operating systems included RTOS (Real-Time Operating System), MSOS 5 (Mass Storage Operating System), and TIMESHARE
Timeshare
A timeshare is a form of ownership or right to the use of a property, or the term used to describe such properties. These properties are typically resort condominium units, in which multiple parties hold rights to use the property, and each sharer is allotted a period of time in which they may use...
3 (time-sharing
Time-sharing
Time-sharing is the sharing of a computing resource among many users by means of multiprogramming and multi-tasking. Its introduction in the 1960s, and emergence as the prominent model of computing in the 1970s, represents a major technological shift in the history of computing.By allowing a large...
system).
"Cyber 18-17" was just a new name for the System 17, based on the 1784 processor. Other Cyber 18s (Cyber 18-05, 18-10, 18-20, and 18-30) had microprogrammable
Microcode
Microcode is a layer of hardware-level instructions and/or data structures involved in the implementation of higher level machine code instructions in many computers and other processors; it resides in special high-speed memory and translates machine instructions into sequences of detailed...
processors with up to 128K words of memory, four additional general registers, and an enhanced instruction set. The Cyber 18-30 had dual processors. A special version of the Cyber 18, known as the MP32, that was 32-bit instead of 16-bit was created for the National Security Agency for crypto-analysis work. The Soviet Union tried to buy several of these systems and they were being built when the US Government cancelled the order. The parts for the MP32 were absorbed into the Cyber 18 production. One of the uses of the Cyber 18 was monitoring the Alaskan Pipeline.
M1000 / C1000 later renamed Cyber 1000 was used as a message store and forward system used by the Federal Reserve System. A version of the Cyber 1000 with its hard drive removed was used by Bell Telephone. This was a RISC processor (Reduced Instruction Set Computer). An improved version known as the Cyber 1000-2 with the Line Termination Sub-System added 256 Zilog Z80 microprocessors. The Bell Operating Companies purchased large numbers of these systems in the mid to late 1980s for data communications. In the late 1980s the XN10 was released with an improved processor (a direct memory access instruction was added) as well as a size reduction from two cabinets to one. The XN20 was an improved version of the XN10 with a much smaller footprint. The Line Termination Sub-System was redesigned to use the improved Z180 microprocessor (the Buffer Controller card, Programmable Line Controller card and two Communication Line Interface cards were incorporated on to a single card). The XN20 was in pre-production stage when the Communication Systems Division was shut down in 1992.
Jack Ralph was the chief architect of the Cyber 1000-2, XN-10 and XN-20 systems. Dan Nay was the chief engineer of the XN-20.
External links
- CDC IBM front end bows (Article in Network World Dec 1, 1986, page 4)
- Cyber documentation at bitsavers.org