A Bus Functional Model or BFM (also known as a Transaction Verification Models or TVM) is a non-synthesizable

Logic synthesis

In electronics, logic synthesis is a process by which an abstract form of desired circuit behavior, typically register transfer level , is turned into a design implementation in terms of logic gates. Common examples of this process include synthesis of HDLs, including VHDL and Verilog...

 software model of an integrated circuit

Integrated circuit

An integrated circuit or monolithic integrated circuit is an electronic circuit manufactured by the patterned diffusion of trace elements into the surface of a thin substrate of semiconductor material...

 component having one or more external buses. The emphasis of the model is on simulating system bus transactions prior to building and testing the actual hardware. BFM's are usually defined as tasks in Hardware description language

Hardware description language

In electronics, a hardware description language or HDL is any language from a class of computer languages, specification languages, or modeling languages for formal description and design of electronic circuits, and most-commonly, digital logic...

s (HDLs), which applies stimulus to the design under test/verification via complex waveforms and protocols. A BFM is typically written in an HDL language such as verilog

Verilog

In the semiconductor and electronic design industry, Verilog is a hardware description language used to model electronic systems. Verilog HDL, not to be confused with VHDL , is most commonly used in the design, verification, and implementation of digital logic chips at the register-transfer level...

, VHDL, SystemC

SystemC

SystemC is a set of C++ classes and macros which provide an event-driven simulation kernel in C++ . These facilities enable a designer to simulate concurrent processes, each described using plain C++ syntax...

, or SystemVerilog

SystemVerilog

In the semiconductor and electronic design industry, SystemVerilog is a combined Hardware Description Language and Hardware Verification Language based on extensions to Verilog.-History:...

.

On one side, it drives and samples low-level signals according to the bus protocol. On the other side, tasks are available to create and respond to bus transactions.

BFMs are often used as reusable building blocks to create simulation test benches, where the signal ports on a design under test are connected to the appropriate BFMs in the test bench for the purpose of simulation.

Transaction Verification Models

BFMs are sometimes referred to as TVMs or Transaction Verification Models. This is to emphasize that bus operations of the model have been bundled into atomic bus transactions to make it easier to issue and view bus transactions. Viewing of bus transactions of TVMs is similar to viewing the output of a protocol analyzer

Protocol analyzer

A "Protocol analyzer" is a tool used to capture and analyze signals and data traffic over a communication channel. Such a channel differs from a local computer bus to a satellite link, that provides a means of communication using a standard communication protocol...

 or bus sniffer.

External references

• Manual and Automatic VHDL/Verilog Test Bench Coding Techniques