26-bit
Encyclopedia
In the ARM processor architecture
, 26-bit refers to the design used in the original ARM processors, where the Program Counter
(PC) and Processor Status Register
(PSR) were combined into one 32-bit register (R15), the status flags filling the high 6 bits and the Program Counter taking up the lower 26 bits.
In fact, because the program counter is always word-aligned the lowest two bits are always zero which allowed the designers to reuse these two bits to hold the processor's mode bits too. The four modes allowed were USR26, SVC26, IRQ26, FIQ26; contrast this with the 32 possible modes available when the program status was separated from the program counter in more recent ARM architectures
.
This design enabled more efficient program
execution, as the Program Counter and status flags could be saved and restored with a single operation. This resulted in faster subroutine
calls and interrupt
response than traditional designs, which would have to do two register loads or saves when calling or returning from a subroutine.
internally, processors prior to the ARM6 had only a 26-bit PC and address bus
, and were consequently limited to 64 MB of addressable memory. This was still a vast amount of memory at the time, but because of this limitation, architectures since have included various steps away from the original 26-bit design.
The ARM6 introduced a 32-bit PC and separate PSR, as well as a 32-bit address bus, allowing 4 GB of memory to be addressed. The change in the PC/PSR layout caused incompatibility with code written for previous architectures, so the processor also included a 26-bit compatibility mode which used the old PC/PSR combination. The processor could still address 4 GB in this mode, but could not execute
anything above address 3FFFFFC (64 MB). This mode was used by RISC OS
running on the Acorn Risc PC
to utilise the new processors while retaining compatibility with existing software.
More recent ARM architectures such as Intel's XScale
have dropped the 26-bit mode altogether.
ARM architecture
ARM is a 32-bit reduced instruction set computer instruction set architecture developed by ARM Holdings. It was named the Advanced RISC Machine, and before that, the Acorn RISC Machine. The ARM architecture is the most widely used 32-bit ISA in numbers produced...
, 26-bit refers to the design used in the original ARM processors, where the Program Counter
Program counter
The program counter , commonly called the instruction pointer in Intel x86 microprocessors, and sometimes called the instruction address register, or just part of the instruction sequencer in some computers, is a processor register that indicates where the computer is in its instruction sequence...
(PC) and Processor Status Register
Status register
A status register or flag register is a collection of flag bits for a processor. An example is the FLAGS register of the x86 architecture....
(PSR) were combined into one 32-bit register (R15), the status flags filling the high 6 bits and the Program Counter taking up the lower 26 bits.
In fact, because the program counter is always word-aligned the lowest two bits are always zero which allowed the designers to reuse these two bits to hold the processor's mode bits too. The four modes allowed were USR26, SVC26, IRQ26, FIQ26; contrast this with the 32 possible modes available when the program status was separated from the program counter in more recent ARM architectures
ARM architecture
ARM is a 32-bit reduced instruction set computer instruction set architecture developed by ARM Holdings. It was named the Advanced RISC Machine, and before that, the Acorn RISC Machine. The ARM architecture is the most widely used 32-bit ISA in numbers produced...
.
This design enabled more efficient program
Computer program
A computer program is a sequence of instructions written to perform a specified task with a computer. A computer requires programs to function, typically executing the program's instructions in a central processor. The program has an executable form that the computer can use directly to execute...
execution, as the Program Counter and status flags could be saved and restored with a single operation. This resulted in faster subroutine
Subroutine
In computer science, a subroutine is a portion of code within a larger program that performs a specific task and is relatively independent of the remaining code....
calls and interrupt
Interrupt
In computing, an interrupt is an asynchronous signal indicating the need for attention or a synchronous event in software indicating the need for a change in execution....
response than traditional designs, which would have to do two register loads or saves when calling or returning from a subroutine.
History
Despite being 32-bit32-bit
The range of integer values that can be stored in 32 bits is 0 through 4,294,967,295. Hence, a processor with 32-bit memory addresses can directly access 4 GB of byte-addressable memory....
internally, processors prior to the ARM6 had only a 26-bit PC and address bus
Address bus
An address bus is a computer bus that is used to specify a physical address. When a processor or DMA-enabled device needs to read or write to a memory location, it specifies that memory location on the address bus...
, and were consequently limited to 64 MB of addressable memory. This was still a vast amount of memory at the time, but because of this limitation, architectures since have included various steps away from the original 26-bit design.
The ARM6 introduced a 32-bit PC and separate PSR, as well as a 32-bit address bus, allowing 4 GB of memory to be addressed. The change in the PC/PSR layout caused incompatibility with code written for previous architectures, so the processor also included a 26-bit compatibility mode which used the old PC/PSR combination. The processor could still address 4 GB in this mode, but could not execute
Execution (computers)
Execution in computer and software engineering is the process by which a computer or a virtual machine carries out the instructions of a computer program. The instructions in the program trigger sequences of simple actions on the executing machine...
anything above address 3FFFFFC (64 MB). This mode was used by RISC OS
RISC OS
RISC OS is a computer operating system originally developed by Acorn Computers Ltd in Cambridge, England for their range of desktop computers, based on their own ARM architecture. First released in 1987, under the name Arthur, the subsequent iteration was renamed as in 1988...
running on the Acorn Risc PC
Risc PC
The RiscPC was Acorn Computers's next generation RISC OS/Acorn RISC Machine computer, launched on 15 April 1994, which superseded the Acorn Archimedes. The Acorn PC card and software allows PC compatible software to be run....
to utilise the new processors while retaining compatibility with existing software.
More recent ARM architectures such as Intel's XScale
XScale
The XScale, a microprocessor core, is Intel's and Marvell's implementation of the ARMv5 architecture, and consists of several distinct families: IXP, IXC, IOP, PXA and CE . Intel sold the PXA family to Marvell Technology Group in June 2006....
have dropped the 26-bit mode altogether.
External links
- Differences Between ARM6 and Earlier ARM Processors
- "Using the Acorn C/C++ Development Environment to write 32-bit RISC OS software" - Details on the architectural changes and converting code between 26-bit and 32-bit.
- http://www.heyrick.co.uk/assembler/32bit.html - Information on converting assembler to 32-bit